The Principle Of Duality States Computer Science Essay

The Principle Of Duality States Computer Science EssayTo simplify a SOP for a Boolean expression using a K map, first base identify all the foreplay combinations that produce an end product of logical system level 1 and place them in their appropriate K map cell. Consequently, all other cells must contain zero (0). Second, assort the adjacent cells that contain 1 in a manner that maximizes the coat of the chemical groups precisely also minimizes the total rate of groups. All 1s in the produce must be embarrassd in a group plain if the group is only adept cell. Third, as individually SOP depot represents an AND expression, each (AND) grouping is written with only the comment uncertains that ar prevalent to the group. Finally, the simplified expression is fashion modeled by ORing each of the (AND) groups. To illustrate permit us consider the function X =first principle+ABC+ABC whose truth table and K map be illustrated below integrity table specifications for a l ogic function may non to include all possible combinations of the input binary digits for the input variables, yet they may still be complete specifications of the logic function for the prescribed application. In these situations certain input combinations will not occur due to the temper of the application. When the input combinations are irrelevant or shadowernot occur, the railroad siding stirs are in the Truth table and the K map are filled with an X and are referred to as dont care maintains.When simplifying K maps with dont care presents, the contents of the shadowy cells (1 or 0) are chosen according to preference. The aim is to en bear-sized group sizes thereby eliminating as m any input variables from the simplified expression as possible. Only those Xs that assist in simplifying the function should be included in the groupings. No additional Xs should be added that would result in additional name in the expression.THE TABULATION METHODThe K-map method acting is convenient as dogged as the number of variables does not exceed five or six, but when the number increases it becomes difficult to habituate this method. The tabulation method overcomes this difficulty, besides it is competent for computer mechanisation. It was first formulated by Quine and later improved by McCluskey. It is also known as the Quine-McCluskey method.The tabular method of simplification consits of both partsDetermination of Prime Impli female genitaliats.Selection of Essential Prime Implicants.The first part is covered in the software provided, the sec part is not. each(prenominal) minterm and its combined cells are included in the Minterm depict, and cerebrate lists techniques are used. link up lists are the best way to manage unknown amount of information at run succession instead of using a large array which is a waste of memory. The record used isPminterm = MintermMinterm = Record effect Word This is to clutches the decimal equivalent of the mintermNu mberOfOnes Byte This is to hold the no. of 1s in the field NumberSelected Boolean used as a beat when this term is selectedCellStr String a string to hold all minterms that form a cell with this term DashPlaceStr String a string to hold the place of the dash Next Pminterm a pointer to the next record to form a linked listEndThe software summons summarise as followsThe user enters the minterms in decimal equivalent.The program sorts minterms in the number of ones included in the binary equivalent (SortMinTerms).Any twain minterms that differ from each other by only one variable are combined (done in FirstTabulation procedure), two minterms fit into this category if the number in the lower group is greater than that in the upper one, and the two numbers differ by a power of 2 e.g. ( 2d = 0010b and 10d = 1010b the remainder is 8d which is a power of 2). Then the two numbers are copied to the second linked list ( First, Second, Vertex Pminterm). This procedure is carried fo r all the minterms. twin(a) groups are copied to second linked list while first one deleted.Then a second tabulation is carried in the SecondTabulation procedure, here each cell contained in the CellStr field of the Minterm record are compared together, a twinned is found if the numbers in one cell are greater than the other one and they differs by a power of 2 e.g. (0,2 and 8,10 differs by 8 which is a power of two) . This procedure is carried for all the records in the second linked list and matching cells are copied to the first linked list, and any incomparable cells are copied to the Vertex linked list. Then the second linked list is deleted.The step 4 is repeated m 1 time where m is the number of inputs, transferring cells between first and second linked lists.The ratiocination linked list and the vertex linked list prime implicants are printed in the ABC equivalent using the WMterm procedure.My program architecture can be used to simplify any number of inputs, but virtua l(a) limitations are in the Number field in the Minterm record which is a word i.e. 16 bits (16 inputs). Bearing in mind as come up the simplified expression is contained in a string which is only 255 characters. around inputs and corresponding turn outputs to try on the programBoolean Expression change Boolean ExpressionF(A,B,C) = S(0,6,7)ABC + ABF(A,B,C) = S(0,4,6,7)BC + AB + ACF(A,B,C,D,E,F) = S(4,5,6,7,36,37,38,39)BCDF(A,B,C,D,E,F,G,H) = S(16,17 up to 31,144,145 up to 159)BCDVARIABLE ENTERED METHOD (VEM)The conventional logic minimisation is time consuming easy only for 4-5 variables. It becomes difficult to solve using conventional K-map method when number of variables goes on increasing. In that case shifting Entered Method will be good idea to use. It represents values of functions in terms of its variables called map entered variables.A new method for obtaining a squash subsumptive general solution of a system of Boolean equations is presented. The method relies on the use of the variable-entered Karnaugh map (VEKM) to achieve nonparallel elimination by successive map folding. It is superior in efficiency and simplicity to methods employing Marquand diagrams or unoriginal Karnaugh maps it requires the construction of significantly smaller maps and produces such maps in a minimization-ready form. Moreover, the method is applicable to general Boolean equations and is not restricted to the two-valued case. combinable attendant Circuits combinable logic circumferences implement Boolean functions. Boolean functions are mappings of input bitstrings to output bitstrings. These circuits are functions of input only.What does that mean? It means that if you feed in an input to a circuit, say, 000, wherefore look at its output, and discover it is, say, 10, then the output will invariably be 10 for that circuit, if 000 is the input. 000 is mapped to 10.If that value were not the same every single time, then the output must not completely depend on 000. Something else must be affecting the output. Combinational logic circuits always depend on input.Another way to go down something that is a function of input is to imagine that you are only allowed to use input variables xk-1,,x0, i.e. data inputs, cm-1,,c0, i.e., control inputs, to write the function. This function can not depend on global variables or other variables.Like combinable logic circuits, a sequential logic circuit has inputs (labelled with x with subscripts) and outputs (labelled with z with subscripts).Unike combinational logic circuits, a sequential logic circuit uses a clock.Also, there is a stripe inside the circuit called State.This box contains liberty chit flops. Assume it has k flip flops. The flip flops basically store a k-bit number representing the current verbalise.The output z is computed ground on the inputs (x with subscripts) and the state coming out of the state box (q with subscripts).The state may be updated at each overconfident clock edge. W hen theres not a tyrannical clock edge, the state remains unchanged.The information needed to update to the state (called the next state) comes from the current state (the current value of q) and the input, which is fed through combinational logic, and fed back into the state box, telling the state box how to update itself.A sequential circuit uses flip flops. Unlike combinational logic, sequential circuits have state, which means basically, sequential circuits have memory.The main difference between sequential circuits and combinational circuits is that sequential circuits compute their output based on input and state, and that the state is updated based on a clock. Combinational logic circuits implement Boolean functions, so they are functions only of their inputs, and are not based on clocks.The S-R LatchA bi persistent multivibrator has two stable states, as indicated by the prefix bi in its name. Typically, one state is referred to as set and the other as reset. The simplest b istable device, therefore, is known as a set-reset, or S-R, hook.To create an S-R latch, we can wire two NOR gates in such a way that the output of one feeds back to the input of another, and vice versa, like thishttp//sub.allaboutcircuits.com/images/04173.pngThe Q and not-Q outputs are supposed to be in reversal states. I say supposed to because making both the S and R inputs equal to 1 results in both Q and not-Q being 0. For this reason, having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0 sets the multivibrator so that Q=1 and not-Q=0. Conversely, making R=1 and S=0 resets the multivibrator in the adversary state. When S and R are both equal to 0, the multivibrators outputs latch in their prior states.The Clocked D-LatchSince the modify input on a gated S-R latch provides a way to latch the Q and not-Q outputs without regard to the status of S or R, we can eliminate one of those inputs to create a multi vibrator latch circuit with no illegal input states. Such a circuit is called a D latch, and its internal logic looks like thishttp//sub.allaboutcircuits.com/images/04181.pngNote that the R input has been replaced with the equilibrize (inversion) of the old S input, and the S input has been renamed to D. As with the gated S-R latch, the D latch will not respond to a signal input if the modify input is 0 it simply stays latched in its last state. When the enable input is 1, however, the Q output follows the D input.Since the R input of the S-R circuitry has been done forward with, this latch has no invalid or illegal state. Q and not-Q are always opposite of one another.Master-Slave Flip-FlopsA master- break ones back turn over is constructed from two seperate riffles. One circuit serves as a master and the other as a slave. The logic diagram of an SR thong is shown in figure below. The master turn around is enabled on the positive edge of the clock pulse CP and the slave fli p-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.http//wearcam.org/ece385/lectureflipflops/flipflops/fig9.gifLogic diagram of a master-slave flip-flopThe timing kin is shown in Figure below and is assumed that the flip-flop is in the choke state prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master.http//wearcam.org/ece385/lectureflipflops/flipflops/fig10.gifTiming relationship in a master slave flip-flopEdge Triggered DevicesAnother eccentric person of flip-flop that synchr onizes the state changes during a clock pulse transition is the edge-triggered flip-flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative edge of the pulse (negative-edge-triggered). The logic diagram of a D-type positive-edge-triggered flip-flop is shown in figure belowhttp//wearcam.org/ece385/lectureflipflops/flipflops/fig11.gifD-type positive-edge triggered flip-flopWhen using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs draw their transitions at the same time, ie., during either the negative edge or the positive edge of the clock pulse.